Integrated circuit for processing digital signal

ABSTRACT

An integrated circuit formed on a single chip, such as a large-scale integration (LSI) chip, which enables a plurality of digital signal processing functions to be performed. A desired digital signal processing function may be selected from among the plurality of available processing functions by the use of a control signal or signals supplied from outside the LSI chip. The LSI chip may include input terminals t1, t2, and t2&#39;; output terminals t3 and t4; and a control signal input terminal t5. Additionally, the LSI chip may further include class sorting circuits, delay and switching circuits, switching circuits, coefficient memories, filter operating circuits, a line delay circuit, and a product sum operating circuit.

TECHNICAL FIELD

The present invention relates to an integrated circuit for processing,for example, a digital image signal.

BACKGROUND ART

For example, in case of constructing a hardware for processing a digitalimage signal as a large scale integration (LSI), one of its methods isto develop and design an exclusive-use LSI corresponding to its processand another method is to use a DSP (Digital Signal Processor) havinggenerality. The DSP comprises a product sum operator, an RAM/ROM, andthe like and can execute digital signal processes of an FFT, a digitalfilter, and the like.

In case of the method of developing and designing the exclusive-use LSI,it is necessary to develop and design LSIs of the number correspondingto the number of kinds of digital signal processes. Although The DSP hasexcellency in generality, there is a problem of a bad efficiency.

DISCLOSURE OF INVENTION

It is, therefore, an object of the invention to provide an integratedcircuit for processing a digital signal in which basic hardwareconstructions are made common and a plurality of functions can berealized by one chip.

According to the invention, there is provided an integrated circuit forprocessing a digital signal in which a plurality of circuit groups andselecting means which can switch at least two states are provided in asingle integrated circuit and the selecting means is selectivelycontrolled by a signal from the outside, characterized in that when theselecting means selects a first selection state, at least a part of theplurality of circuit groups is set to a first connection state and isenabled to perform a first signal processing function in the firstconnection state and, when the selecting means selects a secondselection state, at least a part of the plurality of circuit groups isset to a second connection state different from the first connectionstate and is enabled to perform a second signal processing functiondifferent from the first signal processing function.

The selecting means is controlled by a control signal which is givenfrom the outside of the integrated circuit, thereby switching theconnection states of the plurality of circuit groups. The constructionsof the hardwares in the integrated circuit are made common and theplurality of functions which can be selectively designated by a controlsignal can be realized by an integrated circuit of one chip.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram showing a construction of an embodiment of anintegrated circuit according to the invention; FIG. 2 is a block diagramshowing a construction of another embodiment of an integrated circuitaccording to the invention; FIG. 3 is a block diagram of anup-conversion circuit as one of functions which are realized by anotherembodiment of the invention; FIG. 4 is a schematic diagram forexplaining an up-conversion process; FIG. 5 is a block diagram of anexample of a delay and selecting circuit; FIGS. 6A and 6B are schematicdiagrams which is used for explaining an example of the delay andselecting circuit; FIG. 7 is a block diagram of an example of a classsorting circuit; FIGS. 8A and 8B are schematic diagrams which is usedfor explaining an example of the class sorting circuit; FIG. 9 is ablock diagram of an example of a construction for obtaining coefficientsfor the up-conversion process; FIG. 10 is a flowchart when a learningfor obtaining prediction coefficients is executed by a software process;FIG. 11 is a block diagram of a noise reducer as another one of thefunctions which are realized by another embodiment of the invention;FIG. 12 is a block diagram of an example of a construction for obtainingcoefficients for a noise eliminating process; and FIGS. 13A to 13D areschematic diagrams for explaining the noise eliminating process.

BEST MODE FOR CARRYING OUT THE INVENTION

The invention will be described hereinbelow with reference to thedrawings. FIG. 1 shows a construction of an LSI 1 in an embodiment ofthe invention. Namely, in FIG. 1, a construction surrounded by a brokenline is a construction of the integrated circuit (LSI) 1 of one chip.The LSI 1 has input terminals t1 and t2, output terminals t3 and t4, anda control signal input terminal t5. Although not shown, a power sourceterminal, a test terminal, and the like are actually provided for theLSI 1 in addition to the input/output terminals like an ordinary LSI.

A plurality of circuit groups are formed in the LSI 1. Those are:operating circuit groups 11a and 11b; memories 12a and 12b; product sumoperating circuit groups 13a and 13b; adders 14a and 14b; multipliers15a and 15b; and register groups 16a and 16b. For the circuit groups orcircuits, a switching device for switching inputs/outputs or connectingstates among them (they mean both of a mutual connection among thecircuit groups or circuits and a mutual connection among circuits in thecircuit group) is provided in the LSI 1. In other words, a flow of adigital signal in the LSI 1 and functions of the respective circuitgroups can be controlled by the control signals.

That is, switching devices 21a and 21b are provided in relation to theoperating circuit groups 11a and 11b, switching devices 22a and 22b areprovided in relation to the memories 12a and 12b, and switching devices23a and 23b are provided in relation to the product sum operatingcircuit groups 13a and 13b. A switching device 24 is provided inrelation to the adders 14a and 14b, multipliers 15a and 15b, andregister groups 16a and 16b. Control signals S1 to S7 each consisting ofseveral bits are supplied to the switching devices 21a, 21b, 22a, 22b,23a, 23b, and 24, respectively. The control signals S1 to S7 can besupplied from an external control signal generator (for example,construction to generate a predetermined control signal by a lip switch)through the control signal input terminal t5.

According to the construction of FIG. 1, a construction of predictingprocess by a class sorting can be realized by the control signals S1 toS7. The class sorting prediction process will be more specificallydescribed by an embodiment, which will be described hereinlater. Classsorting circuits based on a level distribution are constructed by theoperating circuit groups 11a and 11b, respectively, linear coupling(filter) operating circuits are constructed by the product sum operatingcircuit groups 13a and 13b, respectively, and memories for storingcoefficients for prediction are constructed by the memories 12a and 12b,respectively. Further, mixing circuits for mixing (or switching)prediction signals from two 1-dimensional filters are constructed by theadders 14a and 14b and register groups 16a and 16b.

The LSI 1 of FIG. 1 can also construct a noise reducer using a classsorting process. The noise reducer has a construction such thatnoise-eliminated outputs formed by a two-dimensional filter operationand a three-dimensional filter operation on the basis of the classsorting are mixed in accordance with motion coefficients. In case of thenoise reducer, by the operating circuit groups 11a and 11b, atwo-dimensional filter circuit is constructed by the product sumoperating circuit group 13a, a three-dimensional filter circuit isconstructed by the product sum operating circuit group 13b, the memoriesfor storing the coefficients for prediction are constructed by thememories 12a and 12b, respectively, and the mixing circuits for mixingthe noise-eliminated signals from the 2-dimensional filter and3-dimensional filter in accordance with the motion coefficients areconstructed by the adders 14a and 14b and register groups 16a and 16b.

FIG. 2 shows another embodiment of the invention. Another embodiment hasa construction which enables a class sorting adapting process in amanner similar to the construction shown in FIG. 1. In FIG. 2, referencenumeral 10 denotes an LSI and the LSI 10 has: input terminals t1, t2,and t2' to which the digital image signals are supplied; terminals t3and t4 from which the digital image signals processed by the LSI 10 areoutputted; and a terminal t5 to which the control signal is supplied.

The image signal from the input terminal t1 is supplied to a classsorting circuit 111a, a delay and selecting circuit 112a, and a linedelay circuit 117. As will be described hereinlater, the class sortingcircuit 111a is constructed to execute a logical operation in order tosort a class of a target pixel as a processing target by a target pixelvalue and a distribution of pixel values around the target pixel value.An output of the class sorting circuit 111a is supplied to a switchingcircuit 113a. The class sorting circuit 111a can output two kinds ofcombinations as combinations of a plurality of pixels which are used forthe class sorting. For example, a class sorting using a plurality ofpixel values in a one-dimensional array and a class sorting using aplurality of pixel values in a two-dimensional array can be executed andone of outputs (class information) of the two class sorting operationsis selected by the switching circuit 113a. The switching circuit 113a isswitched by a control signal from the terminal t5. The selected classinformation is supplied as an address to a coefficient memory 115a.

The delay and selecting circuit 112a is constructed by a register group,a line delay circuit, and a selector. The register is used as a samplingdelay element. The delay and selecting circuit 112a is switched by thecontrol signal from the terminal t5. The delay and selecting circuit112a corrects a time deviation between signals which occurs due todifferent signal processes and generates tap outputs necessary for afilter operation. As tap outputs, a tap output for the one-dimensionalfilter and a tap output for a two-dimensional filter are formed. In eachof the one- and two-dimensional filters, two tap structures can beswitched and respective outputs of the two tap structures are suppliedto a switching circuit 114a. A plurality of tap outputs (pixel data)selected by the switching circuit 114a are supplied to a filteroperating circuit 116a.

Coefficient data from the coefficient memory 115a is also supplied tothe filter operating circuit 116a and a filter output is formed by aproduct sum operation. That is, the tap outputs (a plurality of pixeldata) via the switching circuit 114a and a plurality of coefficientsread out from the coefficient memory 115a are calculated by a linearcoupling, so that a prediction value is produced.

The line delay circuit 117 is a circuit which is constructed by a memoryand causes a delay of one to several lines. An output of the line delaycircuit 117 is supplied to another class sorting circuit 111b.

The class sorting circuit 111b, a delay and selecting circuit 112b, aswitching circuit 113b, a switching circuit 114b, a coefficient memory115b, and a filter operating circuit 116b are provided so as to have aconnecting relation similar to that of the above-mentioned class sortingcircuit 111a, delay and selecting circuit 112a, switching circuit 113a,switching circuit 114a, coefficient memory 115a, and filter operatingcircuit 116a. An image signal from the input terminal t2 is supplied tothe class sorting circuit 111b and delay and selecting circuit 112b.

The switching circuits 113a, 113b, 114a, 114b, and a switching circuit119, which will be described hereinlater, is controlled by the controlsignal from the terminal t5. Prediction (filter) coefficients obtainedby a learning have preliminarily been stored in the coefficient memories115a and 115b, By an initializing operation executed by a master resetpulse which is generated by, for example, a power-on or the like, theprediction coefficients are transferred from an external memory to thecoefficient memories 115a and 115b of the LSI 10.

An output of the filter operating circuit 116a is supplied to a productsum operating circuit 118 and the switching circuit 119. An output ofthe filter operating circuit 116b is supplied to the product sumoperating circuit 118 and is also extracted as an output signal to theoutput terminal t4. An output signal of the product sum operatingcircuit 118 is supplied to the switching circuit 119. When the productsum operating circuit 118 constructs a noise reducer, the outputs of thefilter operating circuits 116a and 116b are mixed on the basis of themotion coefficients which are outputted from the class sorting circuit111b. The switching circuit 119 is switched in accordance with thecontrol signal from the terminal t5 and selects one of the output of thefilter operating circuit 116a and the output of the product sumoperating circuit 118 and the selected output is taken out to the outputterminal t3.

Further, an output signal of the line delay circuit 117 and an imagesignal from an input terminal t2' are supplied to the class sortingcircuit 111b and the delay and selecting circuit 112b. By supplying theimage signals having a time difference of one frame from the inputterminals t2 and t2', the class sorting circuit 111b can perform athree-dimensional class sorting and the delay and selecting circuit 112bcan selectively have a one-, two-, or three-dimensional tap structure.

According to the construction of the foregoing embodiment of theinvention, a plurality of digital signals can be processed by changingthe control signal. A specific example will now be described. First, anexample of applying the invention to an up-conversion process of adigital television signal will be described. An example of theup-conversion such that a digital television signal (called an SDsignal) of a standard resolution is inputted and a separating processfor first doubling the number of pixels in the vertical direction andsubsequent1y doubling the number of pixels in the horizontal directionis executed, thereby forming a digital television signal (called an HDsignal) of a high resolution in which the number of pixels is four timeswill be described here. It is also possible to execute the process inthe horizontal direction first, and then, the process in the verticaldirection.

FIG. 3 shows the LSI 10 constructed so as to perform the up-conversionprocess by the control signal from the terminal t5. In FIG. 3 and FIG.11, which will be described hereinlater, signal lines shown by brokenlines denote signal lines which are wired but are related to signalswhich are not selected by the switching circuits 113a, 113b, 114a, 114b,and 119. The SD signal is supplied to an input terminal 120a and issupplied to the input terminal t1 of the LSI 10 via ahorizontal/vertical scanning line converting circuit 121a. The scanningline converting circuit 121a includes a memory and executes a conversionfrom a horizontal scan (scanning order of television raster) to avertical scan. That is, pixels arranged in the vertical direction atsampling positions are outputted in accordance with the order from thesampling position at the left end of a screen to the right end or theorder from the upper side to the lower side at each of the samplingpositions.

Circuits functioning at the time of the up-conversion will now bedescribed. The class sorting circuit 111a and delay and selectingcircuit 112a are connected to the input terminal t1. The classinformation (code signal) as a result of the 1-dimensional class sortingfrom the class sorting circuit 111a is supplied as an address throughthe switching circuit 113a to the coefficient memory 115a. Coefficientsobtained by the learning have preliminarily been stored in thecoefficient memory 115a. The coefficients read out from the coefficientmemory 115a are supplied to the filter operating circuit (1-dimensionalfilter) 116a.

The filter operating circuit 116a multiplies a plurality of pixel dataof the SD signal and a plurality of coefficients from the coefficientmemory 115a and adds the multiplication results. An output signal of thefilter operating circuit 116 is taken out to the output terminal t3through the switching circuit 119. By the construction between the inputterminal t1 and the output terminal t3, the number of pixels are doubledin the vertical direction. The output signal is returned to an inputterminal 120b of the LSI 10 and is supplied from the input terminal 120bto a vertical/horizontal scanning line converting circuit 121b. Anoutput signal of the scanning line converting circuit 121b is againsupplied to the input terminal t2 of the LSI 10. The scanning lineconverting circuit 121b includes a memory and performs a conversion fromthe vertical scan to the horizontal scan. That is, the output signal ofthe scanning line converting circuit 121b becomes a signal of a scansimilar to that of the television raster.

In a manner similar to the input terminal t1 mentioned above, the classsorting circuit 111b and delay and selecting circuit 112b are connectedto the input terminal t2. Further, a process for doubling the number ofpixels in the horizontal direction is executed by the above-mentionedcircuit blocks, the switching circuit 113b, switching circuit 114b,coefficient memory 115b, and filter operating circuit (1-dimensionalfilter) 116b. Consequent1y, the signal (HD signal) having the pixels ofthe number which is four times in which the number of pixels in each ofthe horizontal and vertical directions is doubled is obtained at theoutput terminal t4.

The up-conversion process will now be described in more detail withrespect to, for example, the process in the vertical direction. FIG. 4shows the relation of pixel arrays among three fields (shown by k-1, k,k+1) which continue with respect to the time. From the relation of aninterlace scan, there is a positional deviation of 0.5 H between a lineposition in the field k and a line position in the previous field k-1(or a line position in the field k+1 subsequent to the field k). In caseof such an interlace scan, the interlace relation is broken when thenumber of lines in each field is merely doubled.

When an interval between the lines in the vertical direction is shown by"1", for example, an HD pixel (shown by a painted circle) yb' is formedat a position of a distance 1/8 above an SD pixel (shown by a blankcircle) x4 and an HD pixel (shown by a painted circle) ya' is formed ata position of a distance 3/8 below the SD pixel x4, thereby enabling thenumber of lines to be doubled while holding the interlace relation. Inthe next field k+1, the HD pixel ya' is formed at a position of adistance 3/8 above the SD pixel and the HD pixel yb' is formed at aposition of a distance 1/8 below the SD pixel. Since the position wherethe HD pixel is formed is switched depending on the field as mentionedabove, it is necessary to also switch the coefficients depending on thefield. The coefficient memory 115a has a memory for separately storingtwo sets of coefficients for forming the HD pixels ya' and yb',respectively, and a switching circuit for switching the two sets ofcoefficients every field.

The order of the SD pixels, for example, in the (k)th field is convertedto the order of x₁, x₂, x₃, . . . by the horizontal/vertical scanningline converting circuit 121a in FIG. 3. Target pixel values y_(a) ' andy_(b) ' are formed by seven successive SD pixels in the time series andtwo sets of coefficients al to a₇ and b₁ to b₇ read out from thecoefficient memory 115a, respectively. That is:

y_(a) '=a₁ x₁ +a₂ x₂ + . . . +a₇ x₇

y_(b) '=b₁ x₂ +b₂ x₃ + . . . +b₇ x₈

The SD pixel value necessary for forming the HD pixel value y_(a) ' andthe SD pixel value necessary for forming the HD pixel value y_(b) ' areoutputted from the delay and selecting circuit 112a and are switched bythe switching circuit 114a and the switched pixel is supplied to thefilter operating circuit 116a. The HD pixel values y_(a) ' and y_(b) 'are calculated by the above-mentioned linear coupling in the filteroperating circuit 116a, thereby deriving a vertical double speed signalin which the number of pixels in the vertical direction is doubled atthe output terminal t3.

On the other hand, in a manner similar to the above, an arithmeticoperation of a 1-dimensional filter is executed by, for example, thevalues of seven SD pixels in the horizontal direction and thecoefficients from the coefficient memory 115a, thereby forming ahorizontal double speed signal in which the number of pixels is doubledin the horizontal direction. For example, in case of the input SD signalof 13.5 MHz, the vertical double speed signal having a sampling rate of27 MHz is generated and the HD signal having a sampling rate of 54 MHzis generated at the output terminal t4 by a horizontal process.

In case of an example of a noise reducer, which will be describedhereinlater, the delay and selecting circuits 112a and 112b generateoutputs of 2-dimensional taps so that the filter operating circuits 116aand 116b execute 2-dimensional filter operations. A 1-dimensional tapstructure and a 2-dimensional tap structure can be switched by, forexample, a construction of FIG. 5.

According to the example, the tap structures are switched depending on acase of the 1-dimensional tap structure (up-conversion) shown in FIG. 6Aand a case of the 2-dimensional tap structure (noise reducer) shown inFIG. 6B. In the 1-dimensional tap structure of FIG. 6A, prediction pixelvalues are calculated by the linear coupling between the values x₁ to x₇of seven pixels on the same line, for instance, on l-1 and thecoefficients. In the 2-dimensional tap structure of FIG. 6B, theprediction pixel values are calculated by the linear coupling betweenthe values of total seven pixels of the values x₂ to x₆ of five pixelson the line l-1 and the values x₁ and x₇ of the upper and lower pixelsof x₄.

In the construction of FIG. 5, SD denotes a sample delay element and LDindicates a line delay element. Since the two line delay elements areconnected in serial, the signals of three lines l, l-1, and l-2 aresimultaneously extracted from the inputs and outputs of the two linedelay elements. Six sample delay elements connected in serial areconnected to the signals of the lines, respectively. Consequent1y,pixels in a two-dimensional region of (three lines×seven pixels) asshown in FIG. 6 are simultaneously obtained from the input and output ofeach of the sample delay elements.

Between the 1-dimensional tap structure and the 2-dimensional tapstructure, the values of the five pixels of x₂ to x₆ are commonly used.It is constructed that with respect to x₁ and x₇, a necessary value isselected in correspondence to each tap structure by two selectors. Asmentioned above, the delay and selecting circuit 112a can switch the1-dimensional tap structure and the 2-dimensional tap structure inaccordance with the selector control signal while commonly using manydelay elements. Although the delay and selecting circuit 112b also has aconstruction similar to that shown in FIG. 5, a 3-dimensional tapstructure can be also used by also inputting an output which is delayedby one frame from the input terminal t2'.

The coefficients stored in the coefficient memories 115a and 115b havepreliminarily been obtained by a learning and written by an initializingoperation. The coefficient is decided every class of the target pixel.For example, y_(a) ' and y_(b) ' indicate the data of the target pixelin FIG. 4. One of the class sorting methods uses patterns of the leveldistribution of input signals around the target pixel. For example, inFIG. 4, the class is sorted on the basis of the patterns of the leveldistribution of three pixel data (SD signals) around the target pixel.

Since the pixel data is generally quantization data of eight bits, incase of three pixels, the data has (8×3=24 bits). The number of all ofthe combinations of 24 bits is equal to 2²⁴. The number of classes isenormous, so that a hardware such as a memory or the like for storingthe coefficients is complicated. By compressing the number of bits ofeach pixel which are used for the class sorting, the class sortingcircuits 111a and 111b set the number of classes to proper values.

One of methods of compressing the number of bits of each pixel which isreferred to for the class sorting is to normalize the pixels in thelevel direction. As an example, an average value of the three pixelswhich are referred to is obtained and the peripheral pixels arecompressed from eight bits to one bit in accordance with the magnitudefor the average value. That is, in case of a value larger than theaverage value, `1` is allocated and in case of a value smaller than theaverage value, `0` is allocated. Thus, class information is indicated bya code signal of three bits.

FIG. 7 shows an example of the class sorting circuit 111a. As shown inFIG. 8B, nine pixels included in a 2-dimensional area of (3 lines×3pixels) are simultaneously outputted by two line delay elements (LD) andtotal six sample delay elements (SD) provided every two elements withrespect to each line data. As a method of the class sorting, there are1-dimensional class sorting, 2-dimensional class sorting, and3-dimensional class sorting. In a noise reducer, which will be describedhereinlater, processes of the 2-dimensional class sorting and3-dimensional class sorting are necessary.

In the 1-dimensional class sorting, as shown in FIG. 8A, threesuccessive pixels (x₁, x₂, and x₃) on a time series (the same line) areused. In the 2-dimensional class sorting, nine pixels in the2-dimensional area of (3 lines×3 pixels) are used as shown in FIG. 8B.By using an image signal of one frame before, the 3-dimensional classsorting can be executed. In the example of FIG. 7, the 1-dimensionalclass sorting and the 2-dimensional class sorting can be switched.

In case of the 1-dimensional class sorting using three pixels, a gatecircuit is turned off, the sum (=x₁ +x₂ +x₃) of the values of the threepixels is supplied to an ROM, and the ROM generates an average value Avof the three pixel values. In case of the 2-dimensional class sortingusing nixe pixels, the gate circuit is turned on, the sum (=x₁ +x₂ +x₃ +. . . +x₉) of the values of the nine pixels is supplied to the ROM, theROM generates an average value of the values of the nine pixels as anaverage value Av.

The average value from the ROM and the value of each pixel are comparedby a comparison circuit and a comparison output which is equal to `1`when the pixel value is larger than the average value and is equal to`0` when the pixel value is equal to or less than the average value,that is, the class information is generated. In the construction of FIG.7, by controlling the gate circuit and the ROM, either one of the1-dimensional class sorting and the 2-dimensional class sorting can beexecuted.

As another method of normalization, an ADRC can be also used. The ADRCis a process such that a dynamic range DR and a minimum value MIN of aplurality of pixels are detected, the minimum value MIN is subtractedfrom the value of each pixel, the value obtained by subtracting theminimum value is divided by the dynamic range DR, and the quotient isrounded to an integer.

A case of a 1-bit ADRC will be described as an example. A maximum valueMAX and the minimum value MIN among the three pixels are detected andthe dynamic range DR (=MAX-MIN) is calculated. The minimum value MIN issubtracted from the value of each pixel and the value from which the MINwas subtracted is divided by the dynamic range DR. The quotient of thedivision is compared with 0.5. When the quotient is equal to or largerthan 0.5, `1` is set. When the quotient is less than 0.5, `0` is set.According to the 1-bit ADRC, a result that is substantially the same asthat of the above case of comparing the average value and the value ofeach pixel is obtained. In case of a 2-bit ADRC, the value from whichthe minimum value was subtracted is divided by a quantization step widthcalculated by DR/2².

A learning for obtaining the coefficients to be stored in thecoefficient memories 115a and 115b, will now be described. FIG. 9 showsa construction at the time of a learning for deciding the coefficientswhich are stored in the coefficient memory 115a. Since the coefficientsto be stored in the coefficient memory 115b, are also decided in amanner similar to the above, its description is omitted here. In FIG. 9,the HD signal which was vertical/horizontal scanning converted issupplied to an input terminal shown by reference numeral 41 and thenumber of pixels is decimated to the half by a decimating filter 42. Anoutput signal of the decimating filter 42 is supplied to a coefficientdeciding circuit 43 and a class sorting circuit 44. The class sortingcircuit 44 decides a class of the target pixel by using peripheralpixels in a manner similar to the class sorting circuit 111a. A classcode from the class sorting circuit 44 is supplied to the coefficientdeciding circuit 43 and a memory 45, respectively.

The coefficient deciding circuit 43 decides coefficients such as tominimize a square sum of an error between the prediction value which isformed by the linear coupling and its true value. The HD signal which issupplied to the input terminal 41 is supplied as a true value of thetarget pixel to the coefficient deciding circuit 43. The coefficientdeciding circuit 43 decides the best prediction coefficient by a methodof least squares. The decided coefficient is stored into the memory 45.A storing address is indicted by a class code from the class sortingcircuit 44.

An operation for deciding the coefficient by a software process will nowbe described with reference to FIG. 10. A control of a process is firststarted from step 51. In a formation of learning data in step 52,leaning data corresponding to a known image is formed. In a datafinishing process in step 53, if a process of all of the inputted data,for example, the data of one frame has been finished, the processingroutine advances to a prediction coefficient decision in step 56. If theprocess is not finished, the control is shifted to a class decision instep 54.

The class decision in step 54 is a step of executing the class decidingprocess with respect to the above-mentioned target pixel and forming theclass code for indicating the class. In a formation of a normal equationin next step 55, a normal equation, which will be described hereinlater,is formed. After completion of the processes of all of the data, thecontrol is shifted from the data finishing process in step 53 to step56. In the prediction coefficient decision in step 56, an equation (8),which will be expressed hereinlater, is solved by using a matrixsolution, thereby deciding the coefficient. In a prediction coefficientstoring process in step 57, the prediction coefficient is stored intothe memory 45 and the control of the learning process is finished instep 58.

The processes in step 55 (normal equation formation) and step 56(prediction coefficient decision) in FIG. 10 will be described in moredetail. At the time of the learning, a true value (y) of the targetpixel is known. When a correction value of the target pixel is set to y'and values of the pixels around the target pixel are set to x₁ to x_(n),the linear coupling of (n) taps by coefficients w₁ to w_(n)(corresponding to the above-mentioned a₁ to a_(n) or b₁ to b_(n)) is setevery class as follows:

    y'=w.sub.1 x.sub.1 +w.sub.2 x.sub.2 + . . . +w.sub.n x.sub.n(1)

w_(i) is an undetermined coefficient before the learning.

The learning is performed every class as mentioned above and when thenumber of data is equal to (m), the following equation is obtained inaccordance with the equation (1).

    Y.sub.j '=w.sub.1 x.sub.j1 +w.sub.2 x.sub.j2 + . . . +w.sub.n x.sub.jn(2)

(where, j=1, 2, . . . m)

When m>n, since w_(i) to w_(n) are not decided unconditionally, elementsof an error vector E are defined as:

    e.sub.j =y.sub.j -(w.sub.1 x.sub.j1 +w.sub.2 x.sub.j2 + . . . w.sub.n x.sub.jn)                                                 (3)

(where, j=1, 2, . . . m)

thereby obtaining a coefficient which minimizes the following equation(4). ##EQU1##

This is a solution by what is called a method of least squares. Now, apartial differential coefficient by w_(i) in the equation (4) isobtained. ##EQU2##

Since it is sufficient to decide w_(i) so that the equation (5) is equalto zero, by setting ##EQU3## a matrix is used as follows: ##EQU4## Theequation is generally called a normal equation. When the equation issolved with respect to w_(i) by using a general matrix solution such asa sweep-out method or the like, the prediction coefficients w_(i) areobtained. The prediction coefficients w_(i) are stored into the memory45 by using the class code as an address.

The up-conversion based on the class sorting adapting process is notlimited to the above example but various constructions can be also used.For example, it is also possible that the prediction value itself haspreliminarily been obtained by the learning and can be stored in thememory. The value of the HD pixel can be also obtained by the2-dimensional or 3-dimensional process instead of the 1-dimensionalprocess.

Another example of the signal process circuit constructed by the LSI 10shown in FIG. 2 will now be described. Another example relates to adigital noise reducer constructed as shown in FIG. 11 by the setting ofthe control signal.

In FIG. 11, a digital video signal including noises is supplied to aninput terminal shown by reference numeral 122. The input video signal issupplied to the input terminals t1 and t2 of the LSI 10 and a framememory 123. A video signal of the preceding frame from the frame memory123 is supplied to the input terminal t2' of the LSI 10.

The video signal of the present frame from the input terminal t1 issupplied to the class sorting circuit 111a delay and selecting circuit112a, and line delay circuit 117, respectively. The video signal of thepresent frame supplied to the input terminal t2 is supplied to the classsorting circuit 111b and delay and selecting circuit 112b, respectively.The line delay circuit 117 is provided for simultaneously outputtingdata of a plurality of adjacent lines which is adjacent to the data inthe order of the raster scanning. An output signal of the line delaycircuit 117 is supplied to the class sorting circuits 111a and 111b anddelay and selecting circuits 112a and 112b, respectively. The videosignal of the preceding frame supplied to the input terminal t2' issupplied to the class sorting circuit 111b and delay and selectingcircuit 112b, respectively.

The class information (code signal) obtained by the class sortingcircuit 111a is supplied as an address to the coefficient memory 115athrough the switching circuit 113a and the class information obtained bythe class sorting circuit 111b is supplied as an address to thecoefficient memory 115b through the switching circuit 113b. Thecoefficients preliminarily obtained by the learning have been stored inthe coefficient memories 115a and 115b and the coefficient read out incorrespondence to the class information is supplied to the filteroperating circuit 116a functioning as a 2-dimensional filter and thefilter operating circuit 116b functioning as a 3-dimensional filter,respectively.

The filter operating circuit (2-dimensional filter) 116a forms thenoise-eliminated pixel data on a unit basis of a 2-dimensional blockconsisting of a plurality of adjacent pixels in the present frame. Thefilter operating circuit (3-dimensional filter) 116b forms thenoise-eliminated pixel data on the unit basis of a 3-dimensional blockconsisting of a plurality of pixels in the present and preceding frames.

The video signals from which noises are eliminated are supplied from thefilter operating circuits 116a and 116b to the product sum operatingcircuit 118. A composite video signal from the product sum operatingcircuit 118, namely, the digital video signal from which noises areeliminated is extracted to the output terminal t4 through the switchingcircuit 119. The product sum operating circuit 118 weights and adds theoutput signal of the filter operating circuit (2-dimensional filer) 116aand the output signal of the filter operating circuit (3-dimensionalfilter) 116b by a motion coefficient (K). The motion coefficient (K) isformed by the class sorting circuit 111b.

The class sorting circuit 111a executes the 2-dimensional class sorting.That is, the class of the target pixel is decided on the basis of thepattern of the level distribution of the blocks around the target pixel.On the other hand, the class sorting circuit 111b executes a3-dimensional class sorting. Although the 3-dimensional class sortingcan be executed on the basis of the pattern of the level distribution ofthe 3-dimensional blocks, in order to generate the motion coefficient(K), the class sorting based on the result of the motion detection ispreferable.

As one of the known motion detecting methods, what is called a gradientmethod can be used. This is a method of obtaining a motion amount byusing a frame difference and gradient information (a sampling differencein the horizontal direction and a line difference in the verticaldirection) with respect to all of the pixels in the motion area. When agradient portion of the video signal is moved, a frame difference ΔF(obtained by subtracting a corresponding pixel value of the precedingframe from the pixel value of the present frame) and a samplingdifference ΔE (obtained by subtracting the value of the previous pixelfrom the value of the present pixel) E are obtained. A magnitude of amotion amount v1 in the horizontal direction is obtained from anintegration value Σ|ΔF| in a motion area of an absolute value |ΔF| ofthe frame difference ΔF and an integration value Σ|ΔE | in a motion areaof an absolute value |ΔE| of the sampling difference ΔE. That is,

|v1|=Σ|ΔF|/Σ.vertline.ΔE|

The direction of the motion can be obtained from the relation betweenthe polarity of the frame difference ΔF and the polarity of the samplingdifference ΔE. The motion in the vertical direction can be also detectedin a manner similar to the above.

The class sorting circuit 111b obtains the motion amount by, forexample, the above-mentioned gradient method and generates the motioncoefficient (K) in accordance with the motion amount. The class sortingis executed on the basis of the frame difference ΔF (or |ΔF|) and thesampling difference ΔE (or |ΔE|). In this case, the class sorting isexecuted so as to form the proper number of classes by using the valuesobtained by normalizing values of the frame difference and the samplingdifference.

The 2-dimensional process will be described as an example with respectto the above noise reducer. The coefficients obtained by the learninghave preliminarily been stored in the coefficient memory 115a. FIG. 12shows a construction at the time of the learning and the digital videosignal including noises is supplied to an input terminal shown byreference numeral 71. The input signal is supplied to a noise reducer 72and a block forming circuit 73. The noise reducer 72 eliminates noisesin the input signal. As an example, a noise reducer using a memory of(N) frames for forming an average value of images of (N+1) frames can beused. That is, since noises are generally random, the noises areeliminated by the averaging.

An output signal (noise reduction signal) of the noise reducer 72 issupplied to a block forming circuit 74. The block forming circuits 73and 74 are time series converting circuits for converting the order ofthe raster scanning into data in the order of blocks. An output signalof the block forming circuit 73 is supplied to a class sorting circuit75. The class sorting circuit 75 decides the class of the target pixelon the basis of the level distribution in the blocks while setting thetarget to the center. The class information from the class sortingcircuit 75 is supplied to a coefficient deciding circuit 76 and a memory77.

An input signal and a noise reduction signal are supplied from the blockforming circuits 73 and 74 to the coefficient deciding circuit 76. Thecoefficient deciding circuit 76 decides the best coefficient by themethod of least squares in a manner similar to the above-mentionedcoefficient decision in case of the up-conversion. That is, when theprediction value of the target pixel is generated by the linear couplingbetween the plurality of pixels (pixels of the input signal) in theblocks around the target pixel and the plurality of coefficients, thecoefficient to minimize the error between the prediction value and thevalue of the corresponding pixel in the noise reduction signal isdecided. The decided coefficient from the coefficient deciding circuit76 is written into an address of the memory 77 which is designated bythe class information.

The block forming circuit 73 forms, for example, a block EL1 of a sizeof (3×3) by setting the pixel x₁ to the center as shown in FIG. 13A. Onthe other hand, the block forming circuit 74 forms a block BL11 of asize of (3×3) by setting the pixel y₁ as a center as shown in FIG. 13B.The pixels x₁ and y₁ are pixels at corresponding positions in images.The pixel x₁ includes noises and the noises are reduced in the pixel y₁.Next blocks BL2 and BL12 are blocks which are obtained by shifting theboundary of the blocks BL1 and BL11 by one pixel as shown in FIGS. 13Cand 13D and each of pixels x₂ and y₂ is set to the center.

As mentioned above, by shifting the boundary of the block, a number ofdata for learning is collected and the coefficient is decided by theflowchart of FIG. 10 and the above-mentioned processes. Thus, when theblock BL1 of the input signal shown in FIG. 13A is given, the predictionvalue formed by the linear coupling between the values of eight pixels(values of the pixels except the target pixel x₁) in the block BL1 andeight coefficients is substantially the same as the value y₁ of thepixel including no noise. Thus, the noises of the target pixel x₁ areeliminated.

In addition to the class sorting and filter operation, the filteroperating circuit (3-dimensional filter) 116b executes the noiseeliminating process in a manner similar to the above-mentioned filteroperating circuit (2-dimensional filter) 116a. Since the motioncoefficient (K) corresponds to the motion amount, an output signal ofthe filter operating circuit 116a is multiplied by the coefficient (K),an output signal of the filter operating circuit 116a is multiplied by acoefficient (1-K), and the signals multiplied by those coefficients areadded. That is, since a correlation of images in the time direction issmall when the motion amount is large, a weight of the output of thefilter operating circuit 116a is set to be large.

Although the specific examples of the up-conversion and the noisereducer have been described, they can be controlled by the controlsignal so as to make functions of the digital signal process other thanthem effective. In the example of the digital image signal process usingthe class sorting adapting process, an interpolating circuit forinterpolating the pixels which were decimated by a sub-sampling, aforming circuit of a key signal in a digital chroma key apparatus, andthe like can be constructed.

The invention as mentioned above is not limited to a specific functionlike an exclusive-use LSI and a range of the functions to be realized islimited to a certain extent like the class sorting adapting process inthe foregoing embodiment. Therefore, the efficient process can beexecuted although there is not a sufficient generality like a DSP.

We claims:
 1. An integrated circuit for processing a digital signal, in which a plurality of circuit groups and a number of selecting devices which can switch at least two states are provided in a single integrated circuit and said number of selecting devices are selectively controlled by a control signal which is indicative of a desired signal processing function to be performed by the integrated circuit and which is supplied from outside the integrated circuit,wherein when said number of selecting devices provided in said single integrated circuit select a first selection state, at least a part of said plurality of circuit groups is set to a first connecting state and is enabled to perform a first signal processing function in said first connection state and, when said number of selecting devices provided in said single integrated circuit select a second selection state, at least a part of said plurality of circuit groups is set to a second connection state different from said first connection state and is enabled to perform a second signal processing function different from said first signal processing function in said connection state.
 2. An integrated circuit for processing a digital signal according to claim 1, in which the first signal processing function involves changing a resolution of said digital signal and the second signal processing function involves noise reduction.
 3. An integrated circuit for processing a digital signal, in which a plurality of circuit groups and a number of selecting devices which can switch at least two states are provided in a single integrated circuit and said number of selecting devices are selectively controlled by a control signal which is indicative of a desired signal processing function to be performed by the integrated circuit and which is supplied from outside the integrated circuit,wherein when said number of selecting devices provided in said single integrated circuit select a first selection state, at least a part of said plurality of circuit groups is set to a first connection state and is enabled to perform a first signal processing function in said first connection state and when said number of selecting devices provided in said single integrated circuit select a second selection state, at least a part of said plurality of circuit groups is set to a second connection state different from said first connection state and is enabled to perform a second signal processing function different from said first signal processing function in said connection state, and wherein at least a part of said plurality of circuit groups is set to have a circuit function which is different in accordance with the selection state of said number of selecting devices, thereby switching the signal processing functions of the whole integrated circuit.
 4. An integrated circuit for processing a digital signal according to claim 2,characterized in that said plurality of circuit groups comprise: first and second filter operating means; means for supplying tap outputs to said first and second filter operating means; means for sorting a class of pixel data which is predicted by said first and second filter operating means, respectively; and a memory for giving filter coefficients to said first and second filter operating means in correspondence to class information from said class sorting means, respectively.
 5. An integrated circuit for processing a digital signal according to claim 4, in which one of the selection states is one of a one-dimensional digital filter, a 2-dimensional digital filter, and a 3-dimensional digital filter.
 6. An integrated circuit for processing a digital signal according to claim 4,characterized in that as a tap output which is given to one of said first and second filter operating means, it is enabled to switch at least a one-dimensional tap output and a two-dimensional tap output.
 7. An integrated circuit for processing a digital signal according to claim 4,characterized in that as a class sorting for generating a coefficient which is given to one of said first and second filter operating means, it is enabled to switch at least a one-dimensional class sorting and a two-dimensional class sorting.
 8. An integrated circuit for processing a digital signal according to claim 2, in which the first signal processing function involves chancing a resolution of said digital signal and the second signal processing function involves noise reduction.
 9. An integrated circuit for processing a digital signal having a plurality of circuit groups and a number of selecting devices for selecting at least two states which are provided in a single integrated circuit formed on a single chip, said number of selecting devices being selectively controlled by a control signal which is indicative of a desired signal processing function to be performed by the integrated circuit and which is supplied from outside said chip such that when said number of selecting devices provided in said single integrated circuit formed on said single chip select a first selection state, at least a part of said plurality of circuit groups is set to a first connection state and is enabled to perform a first signal processing function in said first connection state and, when said number of selecting devices provided in said single integrated circuit formed on said single chip select a second selection state, at least a part of said plurality of circuit groups is set to a second connection state different from said first connection state and is enabled to perform a second signal processing function different from said first signal processing function in said first connection state.
 10. An integrated circuit for processing a digital signal having a plurality of circuit groups and a number of selecting devices for selecting at least two states which are provided in a single integrated circuit formed on a single chip, said number of selecting devices being selectively controlled by a control signal which is indicative of a desired signal processing function to be performed by the integrated circuit and which is supplied from outside said chip such that when said number of selecting devices provided in said single integrated circuit formed on said single chip select a first selection state, at least a part of said plurality of circuit groups is set to a first connection state and is enabled to perform a first signal processing function in said first connection state and when said number of selecting devices provided in said single integrated circuit formed on said single chip select a second selection state, at least a part of said plurality of circuit groups is set to a second connection state different from said first connection state and is enabled to perform a second signal processing function different from said first signal processing function in said first connection state, and in which at least a part of said plurality of circuit groups has a circuit function which is set in accordance with the selection state of said number of selecting devices so as to set the signal processing functions of the entire integrated circuit. 